Modeling device isolation in high-density CMOS

Extensive two-dimensional (2-D) modeling has been performed to study device isolation in high density CMOS. Isolation breakdown mechanisms consisting of surface inversion and lateral punchthrough have been analyzed for various isolation spacings between an n- and a p-channel transistor. The modeling results suggest that through a careful process and device design, adequate device isolation can be achieved for a 2-µm n+-to-p+ spacing using conventional field isolation.