Title :
An Augmented Iterative Array for High-Speed Binary Division
Author :
Cappa, Maurus ; Hamacher, V. Carl
Author_Institution :
Collins Radio Company
Abstract :
An augmented iterative array for binary division (IAD), is described. It uses carry-save reduction and carry-look-ahead principles to achieve high speed. Logic cost and speed comparisons with two other design techniques are presented. An 8-bit prototype model that operates in under 500 ns has been built from commercially available high-speed MSI TTL integrated circuits to verify the feasibility of the IAD scheme.
Keywords :
Division network, iterative array, nonrestoring division.; Costs; Digital arithmetic; Fabrication; Fast Fourier transforms; High speed integrated circuits; Integrated circuit modeling; Iterative algorithms; Logic arrays; Logic design; Prototypes; Division network, iterative array, nonrestoring division.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1973.223680
