Restricted Checking Sequences for Sequential Machines

This paper shows that the imposition of some restrictions on the realization of a sequential machine facilitates the derivation of efficient checking sequences for some machines. Specifically, it is assumed that the state logic or the output logic may be faulty, but both of them cannot be faulty at the same time. This condition is satisfied if there is no shared logic between the state and output logic and at most a single fault in the circuit. It is also assumed that the normal machine has a synchronizing sequence. With these restrictions on the realization, the machine identification approach may be used to derive checking sequences that are often shorter than those without the restrictions and detect a larger set of faults than with the circuit testing approach.