Numerical analysis of heavy ion particle-induced CMOS latch-up

Heavy ion particle-induced CMOS latch-up is analyzed using a two-dimensional transient numerical simulator. The charge funneling effect during the carrier collection process is found to lower the parasitic bipolar emitter-base potential barrier. This parasitic bipolar action is the main factor initiating latch-up. Latch-up susceptibility is then examined as a parameter of the heavy ion particle incident condition.