Pipeline interleaved programmable DSP´s: Architecture

Programmable processors specialized to intensive numerical computation and real-time signal processing are often deeply pipelined. The ensuing gain in throughput is moderated by the difficulty of efficiently programming such processors. Techniques for overcoming this difficulty are effective only for modest amounts of pipelining. This paper proposes applying an old but rarely used architectural approach to the design of single-chip signal processors so that the potential benefits of extensive pipelining can be fully realized. The architectural approach is to interleave multiple processes (or programs) through a single deeply pipelined processor in such a way that the disadvantages of deep pipelining disappear. Instead, the user is faced with the need to construct programs that can execute as concurrent processes. The main advantage is that much more pipelining can be used without aggravating the programming. A specific experimental architecture is outlined. The solution offered is a "system solution" in that architectural performance is considered along with programmability and ease of use. In the companion paper, data flow programming is suggested so that algorithms can be automatically partitioned for concurrent execution. Data flow provides a natural environment in which to build signal processing programs and can be supported efficiently in an architecture of the type described here.