Abstract :
With the advent of field-effect transistor (FET) technology it has become practical and economical to employ complex functions as network primitives. This paper describes a synthesis procedure for diagnosable (all single and multiple faults can be detected) FET networks. A companion procedure for generating tests to detect all faults in the resulting network is also described. This methodology does not guarantee the minimality of the network, however, it is intuitively understandable and easy to apply.
Keywords :
Fault diagnosis, FET network, irredundant function, network synthesis, single and multiple faults.; Boolean functions; FETs; Fault detection; Fault diagnosis; Hardware; Helium; Logic devices; Logic gates; Network synthesis; Testing; Fault diagnosis, FET network, irredundant function, network synthesis, single and multiple faults.;
