DocumentCode
1113389
Title
Design of Two-Level Fault-Tolerant Networks
Author
Pradhan, Dhiraj K. ; Reddy, Sudhakar M.
Author_Institution
Department of Computer Science, University of Saskatchewan
Issue
1
fYear
1974
Firstpage
41
Lastpage
48
Abstract
Some new techniques for the synthesis of fault-tolerant two-level combinational networks are presented. Two classes of faults are defined, 1) critical faults and 2) subcritical faults. Critical fauls are the class of faults that cannot be tolerated by any two-level networks. Necessary conditions for synthesis of networks tolerating subcritical faults are developed. As a result it is established that the conditions required for tolerating faults in the logic elements and those required for tolerating faults in the primary inputs are significantly different. Several design techniques are presented and it is shown that if we restrict our class of faults, then certain normally assumed conditions on redundancy can be relaxed. A class of hazards is defined. It is shown that the synthesis of certain hazard-free realizations is equivalent to the fault-tolerant realization, and also an upper bound on the redundancy of the fault-tolerant realization is derived.
Keywords
Critical faults, fail-safe logic, fault masking, Hamming distance, k-static hazards, primary input faults, static hazards, subcritical faults, sum-of-prime implicants form, two-level realizations, unate functions.; Circuit faults; Cities and towns; Combinational circuits; Error correction; Fault tolerance; Hazards; Logic circuits; Network synthesis; Redundancy; Upper bound; Critical faults, fail-safe logic, fault masking, Hamming distance, k-static hazards, primary input faults, static hazards, subcritical faults, sum-of-prime implicants form, two-level realizations, unate functions.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1974.223775
Filename
1672368
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