The Effects of Races, Delays, and Delay Faults on Test Generation

Test sequences constructed by most test generation procedures often create time dependent results when applied to a circuit. These dependencies often invalidate the test. The main cause for this situation is that the test generation procedures and circuit models employed do not take into account many aspects of delay associated with a circuit. In this paper we present modeling techniques to be used by conventional test generation procedures to alleviate some of these problems. These models include the cases of equal, unequal and ambiguous delay values. Both inertial and transport delays are considered. Both static and dynamic output behavior is studied, though we restrict inputs to fundamental mode operation. Finally, a new type of fault, caUed a delay fault, is introduced, and a model developed so that a test to detect this class of fault can be generated via conventional test generation techniques. In summary, this paper attempts to outline procedures and identify problem areas so that test generation is more of a science rather than a hit and miss process, and so that the correctness of results need not always be verified via simulation or physical fault injection.