DocumentCode
1113950
Title
Accurate technique for CV Measurements on SOI structures excluding parasitic capacitance effects
Author
Lee, Jong-Hyun ; Cristoloveanu, Sorin
Author_Institution
Institut National Polytechnic de Grenoble, Grenoble, France
Volume
7
Issue
9
fYear
1986
fDate
9/1/1986 12:00:00 AM
Firstpage
537
Lastpage
539
Abstract
A simple technique is proposed to determine accurate CV curves free from the influence of parasitic capacitance which is inherent to silicon-on-insulator (SOI) structures. The method is based on capacitance measurements between the various terminals and their interpretation according to an appropriate equivalent circuit. Typical results obtained for a mesa-isolated SIMOX capacitor are given.
Keywords
Capacitance measurement; Capacitors; Equivalent circuits; Helium; Integrated circuit interconnections; Microelectronics; Parasitic capacitance; Semiconductor films; Silicon on insulator technology; Substrates;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1986.26464
Filename
1486287
Link To Document