DocumentCode
1114053
Title
Sub-400-ps ISL circuits
Author
Chuang, Ching-Te ; Li, G.P. ; Moy, D. ; Hackbarth, E. ; Cressler, J.D. ; Brodsky, S.B. ; Basavaiah, S.
Author_Institution
IBM T. J. Watson Research Center, Yorktown Heights, NY
Volume
7
Issue
10
fYear
1986
fDate
10/1/1986 12:00:00 AM
Firstpage
564
Lastpage
566
Abstract
This paper describes advanced Integrated-Schottky-Logic (ISL) circuits featuring double-poly self-alignment, "free" epi-base lateral p-n-p clamp, self-aligned guard ring Schottky barrier diode, and silicon-filled trench isolation. Using a 0.7-µm-thick epitaxial layer and 1.2-µm minimum dimensions, gate delays of 432 ps (fan-out = 1) and 527 ps (fan-out = 3) are obtained at current levels of 183 and 255 µA/gate, respectively; with nonwalled emitter. With walled emitter (two sides), a gate delay of 382 ps is achieved for fan-out of 3 at a current level of 267 µA/gate.
Keywords
Circuits; Clamps; Current measurement; Histograms; Logic; Propagation delay; Resistors; Ring oscillators; Schottky barriers; Schottky diodes;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1986.26475
Filename
1486298
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