Multiple Match Resolvers: A New Design Method

After a brief review of alternative techniques, this correspondence presents an approach to multiple-match resolver design which is significantly faster than ones which have hitherto been published. The approach involves the repeated use of a standard functional block to build resolver tree structures capable of generating addresses or logic vectors. Several example designs are shown to illustrate the concept, but the basic intent is to provide a method which can be used effectively under many logic family and physical constraints. For activity vectors of N bits, the scheme produces resolvers with speeds of around log2 N unit gate propagation delays.