Title :
On-Set Realization of Fail-Safe Sequential Machines
Author :
Diaz, Michel ; Geffroy, Jean Claude ; Courvoisier, Marc
Author_Institution :
Laboratoire d´´Automatique et d´´Analyse des Systèmes
Abstract :
Fail-safe sequential machines can be constructed in such a way that if a failure happens in the sequential part, the ulterior functioning must carry on outside the code chosen to represent the set of states. This paper presents a study of the failures in the input combinational circuit and of the feasibility conditions of sequential machines with states coded by a k-out-of-n code. The electronic circuit is realized in a classical way (on-set realization) and must obey two hypotheses, 1) no failure on clock line C, and 2) single fault (stuck at 0 or stuck at 1) on other connections than C.
Keywords :
Constraining set, fail-safe sequential machines, k-out-of-n code, on-set realization, predecessor set.; Circuit faults; Circuit synthesis; Clocks; Combinational circuits; Costs; Electrical fault detection; Electronic circuits; Input variables; Network synthesis; Sequential circuits; Constraining set, fail-safe sequential machines, k-out-of-n code, on-set realization, predecessor set.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1974.223875
