Title :
Optimization of Asynchronous Sequential Circuit Realizations
Author :
Sawin, Dwight H., III
Author_Institution :
Naval Electronics Laboratory Center
Abstract :
Tan recently developed a heuristic state assignment algorithm for asynchronous sequential circuits. This note extends Tan´s procedure to include optimization of the output state logic, as well as the next state logic, and single-output-change (SOC) flow tables with DON´T CARE entries. The extended algorithm exhibits the same simplicity of execution as Tan´s procedure.
Keywords :
Asynchronous sequential machines, internal state assignments, logic circuit realizations, single-transition-time (STT) sequential circuit realizations.; Algorithm design and analysis; Bismuth; Cost function; Design optimization; Equations; Heuristic algorithms; Logic circuits; Sequential circuits; Terminology; Asynchronous sequential machines, internal state assignments, logic circuit realizations, single-transition-time (STT) sequential circuit realizations.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1974.223884
