Title :
A new address scheme to improve the display quality of a-Si TFT/LCD panels
Author :
Kaneko, Yoshiyuki ; Tanaka, Yasuo ; Kabuto, Nobuaki ; Tsukada, Toshihisa
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
12/1/1989 12:00:00 AM
Abstract :
A drive scheme for a-Si thin-film-transistor/liquid-crystal-display (TFT/LCD) panels that cancels out the DC voltage of the pixel electrode is described. This addressing scheme comprises a three-level gate pulse and an additional capacitor. The gate pulse level has opposite polarity to the conventional two levels and plays a role in compensating the DC voltage caused by the parasitic capacitance of a-Si TFT panels. The compensating voltage is introduced through an additional capacitor fabricated between a pixel electrode and the next gate line. This method is successfully introduced to a 5-in.-diagonal panel, and improvement of the display quality is observed. The latent image is reduced by this addressing scheme, as is flicker noise. The relation between DC voltage and the latent image is clearly recognized in the display panel. The mechanism of flicker noise caused by DC voltage is also discussed
Keywords :
amorphous semiconductors; elemental semiconductors; flat panel displays; liquid crystal displays; silicon; thin film transistors; 5 in; Si thin film transistor; TFT/LCD panels; addressing scheme; amorphous semiconductors; compensating voltage; display quality; flat panel display; flicker noise; parasitic capacitance; pixel electrode; thin film transistor-liquid crystal display panels; three-level gate pulse; 1f noise; Capacitors; Electrodes; Equivalent circuits; Flat panel displays; Image recognition; Liquid crystal displays; Parasitic capacitance; Thin film transistors; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
