Abstract :
A novel high-performance processor architecture for processing a large number of independent instruction streams is proposed and its operating behavior studied. The proposed processor operates on instruction words in a two-address format (thereby eliminating the "operating registers"), and is organized in a fashion which permits as high degree of internal buffering and pipelining. The processor has the following properties: 1) The hardware cost grows only slightly more than linearly with the overall implementation cost; 2) The overall performance is primarily dependent on the processor wordtime and is only secondarily dependent on the supporting memory cycle time; 3) All instruction stream interfaces with memory occur at special queuing (buffer) units which are used to "unscramble" the instruction streams and continually provide work for subsequent processing elements.
Keywords :
Computer architecture, computer instruction stream models, multiple instruction stream, multiple data stream (MIMD) queued instruction processing, resource-sharing, two-address format.; Computer aided instruction; Computer architecture; Costs; Hardware; Isolation technology; Pipeline processing; Process design; Registers; Resource management; Throughput; Computer architecture, computer instruction stream models, multiple instruction stream, multiple data stream (MIMD) queued instruction processing, resource-sharing, two-address format.;
