DocumentCode
1114913
Title
A WNx gate self-aligned GaAs p-channel MESFET for complementary logic
Author
Woodhead, Jonathan ; Uchitomi, Naotaka ; Kameyama, Atushi ; Ikawa, Yasuo ; Toyoda, Nabuyuki
Author_Institution
University of Sheffield, Sheffield, England
Volume
34
Issue
2
fYear
1987
fDate
2/1/1987 12:00:00 AM
Firstpage
170
Lastpage
174
Abstract
The Schottky barrier of reactively sputtered WNx to p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFET´s were fabricated with WNx gates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FET´s with 2 µm × 24 µm gates were 0.088 mA/V2, consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.
Keywords
Annealing; Delay effects; FETs; Gallium arsenide; Heat treatment; Logic gates; MESFETs; Power dissipation; SPICE; Schottky barriers;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1987.22903
Filename
1486614
Link To Document