Title :
A Note on Easily Testable Realizations for Logic Functions
Author :
Kodandapani, K.L.
Author_Institution :
School of Automation, Indian Institute of Science
fDate :
3/1/1974 12:00:00 AM
Abstract :
It is shown that at most, n + 3 tests are required to detect any single stuck-at fault in an AND gate or a single faulty EXCLUSIVE OR (EOR) gate in a Reed-Muller canonical form realization of a switching function.
Keywords :
Fault detection, Reed-Muller canonical form, stuck-at faults.; Algebra; Circuit faults; Circuit testing; Costs; Electrons; Fault detection; Logic functions; Logic testing; Switching circuits; Switching systems; Fault detection, Reed-Muller canonical form, stuck-at faults.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1974.223935
