Title :
Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization
Author :
Chang, Runzi ; Cao, Yu ; Spanos, Costas J.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
Abstract :
A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the dishing radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.
Keywords :
chemical mechanical polishing; erosion; integrated circuit interconnections; planarisation; semiconductor process modelling; CMP; chemical-mechanical planarization; damascene process; dishing metric; dishing model; dishing radius; electrical effects; erosion; line-splitting; metal dishing; on-chip interconnect optimization; Chemical processes; Chemical technology; Copper; Data analysis; Dielectrics; Planarization; Process design; Semiconductor device modeling; Slurries; Testing; CMP; Chemical–mechanical planarization; damascene process; dishing radius; erosion; line-splitting; metal dishing;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2004.834898
