Title :
Effects of post-deposition annealing on the electrical properties and reliability of ultrathin chemical vapor deposited Ta/sub 2/O/sub 5/ films
Author :
Han, L.K. ; Yoon, G.W. ; Kwong, D.L. ; Mathews, V.K. ; Fazan, P.C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta/sub 2/O/sub 5/ (/spl sim/10 nm) on NH/sub 3/-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800/spl deg/C rapid thermal O/sub 2/ annealing (RTO) for 20 sec followed by rapid thermal N/sub 2/ annealing (RTA) for 40 sec, b) 800/spl deg/C RTO for 60 sec and c) 900/spl deg/C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta/sub 2/O/sub 5//poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics.<>
Keywords :
DRAM chips; annealing; circuit reliability; electric breakdown of solids; elemental semiconductors; integrated circuit technology; rapid thermal processing; silicon; tantalum compounds; 20 to 60 s; 800 to 900 degC; Ta/sub 2/O/sub 5/-Si; Ta/sub 2/O/sub 5//poly-Si interface; capacitance; chemical vapor deposited films; electrical properties; leakage current; over-reoxidation; oxynitride formation; post-deposition annealing; rapid thermal N/sub 2/ annealing; rapid thermal O/sub 2/ annealing; reliability; stacked DRAM applications; time-dependent dielectric breakdown; Capacitance; Chemical vapor deposition; Costs; Electric variables; Electrodes; Leakage current; Random access memory; Rapid thermal annealing; Silicon; Temperature;
Journal_Title :
Electron Device Letters, IEEE
