Title :
Anomalous Ti SALICIDE gate to source/drain shorts induced by dry Si etch during TiSi2 local interconnect formation
Author :
Ting, W. ; Petti, C. ; Radigan, S. ; Ramkumar, K. ; Trammel, P.
Author_Institution :
Cypress Semicond. Corp., San Jose, CA, USA
Abstract :
A new failure mode was observed in a 0.5 μm version of the silicided amorphous-silicon contact and interconnect (SAC) technology. Massive PMOS gate to source/drain shorts were found. The cause is attributed to formation of Ti during the Si etch. The fluorinated Ti surface fails to form adequate TiN diffusion barrier during subsequent rapid thermal annealing (RTA) in N2 or NH3 ambient. Si diffuses from the polycrystalline Si gate and/or the p-type source/drain onto the spacer, reacts with Ti and forms resistive leakage paths. A blanket low-dose, low-energy As implant prior to Ti deposition corrects this problem without adversely changing device characteristics.
Keywords :
CMOS integrated circuits; annealing; etching; integrated circuit technology; metallisation; rapid thermal processing; titanium compounds; 0.5 micron; PMOS; Ti SALICIDE gate to source/drain shorts; TiSi/sub 2/ local interconnect formation; TiSi/sub 2/-SiO/sub 2/-Si; device characteristics; diffusion barrier; dry Si etch; failure mode; metallisation; rapid thermal annealing; resistive leakage paths; silicided amorphous-silicon contact and interconnect technology; Dry etching; Implants; Integrated circuit interconnections; MOS devices; MOSFETs; Sputter etching; Sputtering; Strips; Tin; Wet etching;
Journal_Title :
Electron Device Letters, IEEE
