Characteristics of a new EPROM cell structure with a sidewall floating gate

A new EPROM cell with a sidewall floating gate is proposed and evaluated. The cell structure is similar to that of the usual n-channel MOSFET and has good compatibility, in regard to its fabrication process, with future VLSI devices. The new cell does not require such large coupling capacitance between control gate and floating gate, which results in higher density integration with reduced programming voltages as low as 8 V or less. In actual use of the new cell, the roles of source and drain are reversed in the program mode and in the readout mode. It is shown that the apparent programming characteristics depend on the bias conditions in the readout mode. Very good tolerance to unintentional programming is obtained in the read-out mode, and also in the program mode at half selection.