Field reduction regions for compact high-voltage IC´s

A field reduction region (FRR) is proposed as a means to reduce the chip area of high-voltage IC\´s. This FRR is a lightly doped layer that is fabricated by ion implantation at the circumference of the field region. This layer lowers the surface electric field at the surface of the channel stopper under the interconnection for a given thickness of the SiO2passivation film. By forming the FRR, it is possible either to increase the breakdown voltage or to reduce the field-region length of high-voltage devices used in high-voltage IC\´s. The effects of the FRR are analyzed by a two-dimensional numerical method, and the calculations are confirmed by the experiment. By using this FRR, the area of a diode of the 350-V class is reduced to 38 percent of that of the previous diode without the FRR.