Easily Tested Three-Level Gate Networks for T or More of N Symmetric Functions

This correspondence considers three-level AND/OR gate realizations for T or more of N symmetric functions and gives a design procedure. The procedure can be used to design relatively large networks. The three-level realizations require substantially fewer test patterns for fault detection, gates, and gate inputs than the minimum two-level network. For example, the minimum two-level network for the 3 or more out of 12 functions requires 286 test patterns, 67 gates, and 726 gate inputs while the three-level realization presented requires 27 test patterns, 25 gates, and 96 gate inputs.