Title :
Latchup performance of retrograde and conventional n-well CMOS technologies
Author :
Lewis, Alan G. ; Martin, Russel A. ; Huang, Tiao-Yuan ; Chen, John Y. ; Koyanagi, Mitsumasa
Author_Institution :
Xerox Palo Alto Research Center, Palo Alto, CA
fDate :
10/1/1987 12:00:00 AM
Abstract :
The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+epitaxial material.
Keywords :
CMOS technology; Circuits; Doping; Epitaxial layers; Ion implantation; Isolation technology; Oxidation; Semiconductor device modeling; Silicon; Substrates;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1987.23211
