DocumentCode :
1118374
Title :
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
Author :
Parker, Kenneth P. ; McCluskey, Edward J.
Author_Institution :
Digital Systems Laboratory, Stanford University
Issue :
5
fYear :
1975
fDate :
5/1/1975 12:00:00 AM
Firstpage :
573
Lastpage :
578
Abstract :
A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described in the paper. Finally, a series of examples illustrate the application of the probabilistic approach to the analysis of faulty logic circuits.
Keywords :
Boolean difference, fault detection, general combinational networks, input probability, iterative cells, output probability, probability, signal reliability, symmetric functions, test generation.; Boolean functions; Circuit analysis; Circuit faults; Circuit testing; Electrical fault detection; Logic circuits; Probabilistic logic; Probability; Signal analysis; Signal processing; Boolean difference, fault detection, general combinational networks, input probability, iterative cells, output probability, probability, signal reliability, symmetric functions, test generation.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1975.224264
Filename :
1672857
Link To Document :
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