DocumentCode :
1118435
Title :
Self-aligned UMOSFET´s with a specific on-resistance of 1 mΩ.cm2
Author :
Chang, H.R. ; Black, R.D. ; Temple, V.A.K. ; Tantraporn, Wirojana ; Baliga, B.Jayant
Author_Institution :
General Electric Company Corporate Research and Development Center, Schenectady, NY
Volume :
34
Issue :
11
fYear :
1987
fDate :
11/1/1987 12:00:00 AM
Firstpage :
2329
Lastpage :
2334
Abstract :
This paper describes an improved UMOSFET with an ultralow specific on-resistance. This device utilizes a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 6 µm. This allows for a remarkable increase of channel density and, therefore, reduces the on-resistance per unit area significantly. Experimental devices have been fabricated, and a specific on-resistance of 1.0 mΩ . cm2with a breakdown voltage of 30 V has been achieved. This specific on-resistance is the lowest value ever reported for FET´s.
Keywords :
Contact resistance; Design optimization; Doping; Electric resistance; FETs; Impedance; Lithography; Low voltage; Manufacturing; Thermal stability;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1987.23240
Filename :
1486951
Link To Document :
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