Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks

Author

Agrawal, Prathima ; Agrawal, Vishwani D.

Author_Institution

Department of Electrical Engineering-Systems, University of Southern California

Issue

7

fYear

1975

fDate

7/1/1975 12:00:00 AM

Firstpage

691

Lastpage

695

Abstract

In this paper the random test generation method for large logic circuits is analyzed. Formulas for the detection probability and the number of random input patterns required to complete the test generation with a high probability are obtained for an irredundant fan-out-free combinational network tree consisting of identical n-input NAND gates. The quantitative estimates for the number of random input patterns required for test generation appear to depend upon the number of levels in the circuit and the fan-ins of the gates. Experimental results for actual computer logic circuits are given and show the validity of the approach.

Keywords

Combinational networks, detection probability, fault detection, path sensitizing, probabilistic analysis of logic, random test generation.; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Probabilistic logic; Random number generation; Test pattern generators; Combinational networks, detection probability, fault detection, path sensitizing, probabilistic analysis of logic, random test generation.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/T-C.1975.224289

Filename

1672882