Modelling of propagation delays in the bilevel crossing interconnections on the GaAs-based integrated circuits

A computer-efficient model of the propagation delays in the bilevel crossing interconnections on the GaAs-based very high speed integrated circuits (VHSICs) has been developed. The interconnections on the first and second levels are modelled by a combination of lumped circuit parameters and distributed circuit transmission lines. The ground and coupling capacitances used in the model were determined by the method of moments in conjunction with a Green´s function appropriate for the geometry of the interconnections. Based on the numerical model, several software modules have been developed which have been used to simulate the dependence of the propagation delays on the various interconnection parameters such as its length, width and material resistivity. Modules have also been used to study the dependence of the delays on other design parameters such as the driving transistors´ output resistance, the loading transistor´s input capacitance and the number of crossing lines