Characterization and suppression of drain coupling in submicrometer EPROM cells

The EPROM transistor suffers from a capacitive-coupling-based short-channel effect called drain turn-on or Vdtothat limits the maximum drain voltage. Several measurement techniques are demonstrated to characterize the Vdtoeffect. An analytical model is applied to the problem to estimate the effects of process variations to suppress the phenomenon. The effect of Vdtoon scaling is discussed, and circuit and device design techiques to reduce or eliminate this problem are discussed.