Title :
A model for the trench transistor
Author :
Banerjee, Sanjay ; Bordelon, D. Mark
Author_Institution :
University of Texas, Austin, TX
fDate :
12/1/1987 12:00:00 AM
Abstract :
This paper discusses a model for the trench transistor used in the trench transistor cell (TTC), which is employed in Texas Instruments´ 4-Mbit DRAM. PISCES-II simulations are used to study the unique characteristics that result from the nonuniform doping along the channel and the nonuniform gate oxides in these transistors. The simulations are correlated with experimental data and an analytical description is proposed to qualitatively explain the observed behavior.
Keywords :
Capacitors; Doping profiles; Etching; Instruments; MOSFETs; Process design; Random access memory; Semiconductor process modeling; Silicon on insulator technology; Substrates;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1987.23339
