Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM´s

A two-dimensional power-line selection scheme for an iterative CMOS circuit block is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks in a two-dimensional arrangement and selectively energized by two-dimensional power-line selection. It is shown to be suitable for dual word-line structure, particularly because of its single sub-word line activation. This scheme achieves a very large reduction of active current to one sixteenth, from 116 mA to 22 mA for a 1-V 16-Gb DRAM with dual word-line structure, while maintaining a speed comparable to existing multi-megabit DRAM´s. The proposed scheme is promising for reducing the active power of future multi-gigabit DRAM´s