Title :
A process for a CMOS channel-stop implantation self-aligned to the p-well and p-well active area
Author :
Yamauchi, Noriyoshi
Author_Institution :
Nippon Telegraph and Telephone Corporation, Ibaraki, Japan
fDate :
12/1/1987 12:00:00 AM
Abstract :
A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
Keywords :
Annealing; CMOS process; Chip scale packaging; Large scale integration; Metallization; Radio frequency; Silicon; Sputter etching; Testing; Wet etching;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1987.23351
