Title :
An 8-bit multitask micropower RISC core
Author :
Perotto, J.-F. ; Lamothe, C. ; Arm, C. ; Piguet, C. ; Dijkstra, E. ; Fink, S. ; Sanchez, E. ; Wattenhofer, J.-P. ; Cecchini, M.
Author_Institution :
Centre Suisse d´´Electronique et de Microtechnique SA, Neuchatel, Switzerland
fDate :
8/1/1994 12:00:00 AM
Abstract :
This paper describes a multitask micropower RISC core. A hardware scheduler handles up to four separate tasks in a pseudo-parallel way. Task or context switching is performed at the instruction level and does not need additional instructions. In a 1.5-V low-power 2-μm technology the core area is 5-6 mm2, depending upon the global routing of the complete ASIC. Measured power consumption is 0.2 μA/kHz at 1.5 V with a low-power 8-K word ROM and a 256-byte RAM
Keywords :
application specific integrated circuits; microprocessor chips; reduced instruction set computing; 1.5 V; 2 micron; 8 bit; ASIC; context switching; global routing; hardware scheduler; instruction level; multitask micropower RISC core; power consumption; task switching; Application software; Batteries; Clocks; Energy consumption; Hardware; Low voltage; Microprocessors; Processor scheduling; Reduced instruction set computing; Watches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
