7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT´s

Author

Wang, Zhi-Gong ; Berroth, Manfred ; Nowotny, Ulrich ; Hofmann, Peter ; Hülsmann, Axel ; Köhler, Klaus ; Raynor, Brian ; Schneider, Joachim

Author_Institution

Fraunhofer-Inst. fur Angewandte Festkorperphys., Freiburg, Germany

Volume

29

Issue

8

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

995

Lastpage

997

Abstract

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT´s) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V

Keywords

III-V semiconductors; aluminium compounds; clocks; field effect integrated circuits; gallium arsenide; optical receivers; phase-locked loops; variable-frequency oscillators; 0.3 micron; 7.5 Gbit/s; AlGaAs-GaAs; PLL; bit rate; center oscillating frequency; clock recovery circuit; enhancement/depletion AlGaAs/GaAs quantum well HEMTs; fully-balanced varactorless VCO; optical transmission; power consumption; preprocessing circuit; tuning range; Bit rate; Chromium; Circuit optimization; Clocks; Electron mobility; Frequency; Gallium arsenide; Phase locked loops; Tuning; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.297711

Filename

297711