Velocity saturation in the extrinsic device: a fundamental limit in HFET´s

We have carried out an experimental study revealing that velocity saturation (υ_sat) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET´s. Using AlGaAs/n⁺-InGaAs HFET´s as a vehicle, we find that first g_m and eventually f_T decline at high currents in two stages. Initially, the approach of υ_sat in the extrinsic device causes the small-signal source and drain resistances (r_s and r_d) to rise dramatically, primarily degrading g_m. As the current increases further, the large-signal source and drain resistances (R_s and R_d) grow significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of r_s and r_d, the accompanying increase in gate-drain capacitance forces f_T to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime