DocumentCode
1119924
Title
Solution and Optimization of Systems of Pseudo-Boolean Constraints
Author
Aloul, Fadi A. ; Ramani, Arathi ; Sakallah, Karem A. ; Markov, Igor L.
Author_Institution
American Univ. of Sharjah, Sharjah
Volume
56
Issue
10
fYear
2007
Firstpage
1415
Lastpage
1424
Abstract
Optimized solvers for the Boolean satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, and so forth. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can be handled by integer linear programming (ILP), but generic ILP solvers may ignore the Boolean nature of 0-1 variables. Therefore, specialized 0-1 ILP solvers extend SAT solvers to handle these so-called "pseudo-Boolean" (PB) constraints. This work provides an update on the on-going competition between generic ILP techniques and specialized 0-1 ILP techniques. To make a fair comparison, we generalize recent ideas for fast SAT-solving to more general 0-1 ILP problems that may include counting constraints and optimization. This generalization is embodied in our PB constraint solver and optimizer PBS, which is compared with state-of-the-art CNF and generic ILP solvers. Another aspect of our comparison is the evaluation on 0-1 ILP benchmarks that originate in electronic design automation (EDA) but that cannot be directly solved by an SAT solver. Specifically, we solve instances of the max-SAT and max-ONEs optimization problems, which seek to maximize the number of satisfied clauses and the "true" values over all satisfying assignments, respectively. Those problems have straightforward applications to SAT-based routing and are additionally important due to reductions from max-cut, max-clique, and min vertex cover. Our experimental results show that specialized 0-1 techniques implemented in PBS tend to outperform generic ILP techniques on Boolean optimization problems, as well as on general EDA SAT problems.
Keywords
Boolean algebra; backtracking; computability; integer programming; Boolean satisfiability problem; FPGA planning; FPGA routing; backtrack search; conjunctive normal form; counting constraint; electronic design automation; hardware verification; integer linear programming solver; optimized SAT solver; pseudo-Boolean constraint optimization problem; software verification; Application software; Boolean functions; Constraint optimization; Electronic design automation and methodology; Field programmable gate arrays; Hardware; Integer linear programming; Lead; Minimization; Routing; Backtrack Search; Boolean Satisfiability (SAT); Conjunctive Normal Form (CNF); Global Routing; Integer Linear Programming (ILP); Max-ONE; Max-SAT; Pseudo Boolean (PB);
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2007.1075
Filename
4302712
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