A submicrometer lifted diffused-layer MOSFET

A new lifted diffused-layer (LID) MOSFET has been devised and fabricated, where the major portions of the source/drain (S/ D) diffused layers are placed on top of the field insulator to reduce S/D parasitic capacitances. The primary feature of this MOSFET is that the structure and processing are especially developed for submicrometer gate lengths. The fabricated LID MOSFET with a 0.5-µm gate length and a 10-nm gate oxide thickness showed good electrical characteristics, such as a maximum transconductance of 115 mS/mm and an inverter delay time of 59 ps/stage.