Title :
TOP: an algorithm for three-level combinational logic optimisation
Author :
Dubrova, E. ; Ellervee, P. ; Miller, D.M. ; Muzio, J.C. ; Sullivan, A.J.
Author_Institution :
R. Inst. of Technol., LECS/IMIT, Kista, Sweden
Abstract :
Three-level logic is shown to have a potential for reducing the area over two-level implementations, as well as for a gain in speed over multilevel implementations. A heuristic algorithm TOP is presented, targeting a three-level logic expression of type g/sub 1/spl deg//g/sub 2/, where g/sub 1/ and g/sub 2/ are sum-of-products expressions and ´/sub /spl deg//´ is a binary operation. For the first time, to the authors´ knowledge, this problem is addressed for an arbitrary operation ´/sub /spl deg//´, although several algorithms for specified cases of ´/sub /spl deg//´ have been presented in the past. The experimental results show that, on average, the total number of product-terms in the expression obtained by TOP is about one third of the number of product-terms in the expression obtained by a two-level AND-OR minimiser.
Keywords :
circuit optimisation; combinational circuits; logic design; programmable logic devices; TOP; area reduction; binary operation; heuristic algorithm; multilevel implementations; product-terms expression; sum-of-products expressions; three-level combinational logic optimisation; three-level logic expression; two-level AND-OR minimizer; two-level implementations;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings
DOI :
10.1049/ip-cds:20040159