Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers

Charge-pump phase-locked loops (CP-PLL) are the circuit architecture of choice for embedded frequency synthesis applications. In all situations a frequency synthesis system will generate timing or reference signals for other important system functions. Therefore, it is a key element for satisfactory system level operation and must be verified correctly. The key performance metric for CP-PLLs is often stated in terms of spectral purity or jitter of the generated output signal. However, in a production test environment it can be difficult to assess system performance directly in these terms. For a correctly designed system, output signal degradation can often be related back to deviations or errors introduced during the manufacturing process. In many instances the CP-PLL may be the only analogue block present on a digital SoC (system on chip), and in consequence production test is often focused towards sufficient verification using methods applicable for digital only testers. Direct access DfT (design for test) techniques are often employed to address test requirements for analogue portions of the CP-PLL; however, problems can occur in terms of noise injection and general test access. The paper presents an introductory overview and tutorial providing information relating to key CP-PLL deviations, common direct access DfT extraction methods and the associated problems. In addition, a review of recent significant BIST (built-in-self-test)/DfT test approaches is provided. The focus is on methods that can indirectly validate CP-PLL closed loop performance and be useful in highlighting key jitter or phase noise contributors.