DocumentCode
1121277
Title
N-source/drain compensation effects in submicrometer LDD MOS devices
Author
Hamada, Akemi ; Igura, Yasuo ; Izawa, Ryuichi ; Takeda, Eiji
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
8
Issue
9
fYear
1987
fDate
9/1/1987 12:00:00 AM
Firstpage
398
Lastpage
400
Abstract
N- source/drain compensation effects in LDD devices and p-n junction leakage effects are investigated. In particular, for
µm, these effects will become intrinsic constraints on device minituarization. Furthermore, p-n junction leakage was found to cause refresh failures in dynamic VLSI circuits even under reduced power supply voltage.
µm, these effects will become intrinsic constraints on device minituarization. Furthermore, p-n junction leakage was found to cause refresh failures in dynamic VLSI circuits even under reduced power supply voltage.Keywords
Boron; Circuits; Helium; Hot carrier effects; Impurities; MOS devices; P-n junctions; Power supplies; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1987.26673
Filename
1487223
Link To Document