DocumentCode :
1121980
Title :
Compressible area fill synthesis
Author :
Chen, Yu ; Kahng, Andrew B. ; Robins, Gabriel ; Zelikovsky, Alexander ; Zheng, Yuhong
Volume :
24
Issue :
8
fYear :
2005
Firstpage :
1169
Lastpage :
1187
Abstract :
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low-k dielectrics. To improve manufacturability, and in particular to enable more uniform chemical-mechanical planarization (CMP), it is necessary to insert area fill features into low-density layout regions. Because area fill feature sizes are very small compared to the large empty layout areas that need to be filled, the filling process can increase the size of the resulting layout data file by an order of magnitude or more. To reduce file transfer times, and to accommodate future maskless lithography regimes, data compression becomes a significant requirement for fill synthesis. In this paper, we make the following contributions. First, we define two complementary strategies for fill data volume reduction corresponding to two different points in the design-to-manufacturing flow: compressible filling and post-fill compression . Second, we compare compressible filling methods in the fixed-dissection regime when two different sets of compression operators are used: the traditional GDSII array reference (AREF) construct, and the new Open Artwork System Interchange Standard (OASIS) repetitions. We apply greedy techniques to find practical compressible filling solutions and compare them with optimal integer linear programming solutions. Third, for the post-fill data compression problem, we propose two greedy heuristics, an exhaustive search-based method, and a smart spatial regularity search technique. We utilize an optimal bipartite matching algorithm to apply OASIS repetition operators to irregular fill patterns. Our experimental results indicate that both fill data compression methodologies can achieve significant data compression ratios, and that they outperform industry tools such as Calibre V8.8 from Mentor Graphics. Our experiments also highlight the advantages of the new OASIS compression operators over the GDSII AREF construct.
Keywords :
VLSI; data compression; filling; integrated circuit layout; integrated circuit manufacture; lithography; planarisation; Cu; VLSI manufacturing; area fill synthesis; array reference; chemical-mechanical planarization; compressible filling; data compression; exhaustive search based method; greedy heuristics; low-k dielectrics; manufacturability improvement; maskless lithography; open art-work system interchange standard; smart spatial regularity search; Copper; Data compression; Dielectric materials; Filling; Integer linear programming; Lithography; Manufacturing; Pattern matching; Planarization; Very large scale integration; Dummy fill; GDSII AREF; OASIS repetitions; VLSI manufacturability; fill data compression; greedy method;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.850859
Filename :
1487558
Link To Document :
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