Submicrometer ${\rm Nb}/{\rm Al}{-}{\rm AlO}_{\rm x}/{\rm Nb}$ Integrated Circuit Fabrication Process for Quantum Computing Applications

We have developed a low J_c (100-1000 A/cm²) submicrometer Nb integrated circuit fabrication process for SQUID-based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/Al-AlO_x/Nb trilayer, two Nb wiring layers and two sputtered SiO₂ dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions.