Title :
Worst case crosstalk noise for nonswitching victims in high-speed buses
Author :
Chen, Jun ; He, Lei
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
Abstract :
Considering a RLC interconnect model, we determine switching patterns and switching times of multiple aggressors to generate the worst case crosstalk noise (WCN) for a quiet or a noisy victim. We consider the routing direction as it has a significant impact under the RLC model. When there are no timing window constraints, we show that the commonly used superposition algorithm results in 15% underestimation on average, and propose a new SS + AS algorithm that has virtually the same complexity as the superposition algorithm but has a much improved accuracy. On average, the SS + AS algorithm only underestimates WCN by 3% compared to time-consuming simulated annealing and genetic algorithm. We also show that applying a RC model to the high-speed interconnects in the International Technology Roadmap for Semiconductors 0.10 μm technology virtually always underestimates WCN, and the underestimation can be up to 80%. Furthermore, we extend our algorithm to consider aggressor switching and victim sampling windows. We show that the extended SS + AS algorithm well approximates WCN with 2% underestimation on average. Although the RC model usually severely underestimates WCN with timing window constraints, it does overestimate when both the aggressor switching and the victim sampling windows are small enough. We conclude that the RLC model is needed for accurate modeling of WCN in design in the multigigahertz region.
Keywords :
RLC circuits; crosstalk; inductance; integrated circuit interconnections; integrated circuit modelling; crosstalk noise; genetic algorithm; high speed buses; inductance; interconnect modeling; nonswitching victims; simulated annealing; switching patterns; switching times; Circuit noise; Computer aided software engineering; Crosstalk; Delay; Integrated circuit interconnections; Noise generators; Routing; Sampling methods; Semiconductor device noise; Timing; Crosstalk noise; VLS; inductance; interconnect modeling; signal integrity;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.850823