• DocumentCode
    1123771
  • Title

    Test compression saves bits, cycles, and money

  • Author

    Cheng, Tim

  • Volume
    25
  • Issue
    2
  • fYear
    2008
  • Firstpage
    105
  • Lastpage
    105
  • Abstract
    Test data compression became an active research topic in the late 1990s, and has now become a standard offering within commercial DFT solutions. This issue of IEEE Design & Test features a special issue on the current state of test compression. This issue of D&T also concludes the theme of design and test of RFIC chips (featured in the Jan./Feb. 08 issue), with two additional articles. In addition, this issue features two general-interest articles and an interview with DRAM inventor Bob Dennard.
  • Keywords
    Circuit testing; Clocks; Design for testability; Manufacturing processes; Moore´s Law; Random access memory; Semiconductor device testing; System testing; Test data compression; Variable speed drives; Bob Dennard; DFT; RFIC chips; test compression; test vectors;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2008.52
  • Filename
    4483803
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1123771