DocumentCode
1123817
Title
Historical Perspective on Scan Compression
Author
Kapur, Rohit ; Mitra, Subhasish ; Williams, Thomas W.
Author_Institution
Birla Inst. of Technol., Mesra
Volume
25
Issue
2
fYear
2008
Firstpage
114
Lastpage
120
Abstract
The beginnings of the modern-day IC test trace back to the introduction of such fundamental concepts as scan, stuck-at faults, and the D-algorithm. Since then, several subsequent technologies have made significant improvements to the state of the art. Today, IC test has evolved into a multifaceted industry that supports innovation. Scan compression technology has proven to be a powerful antidote to this problem, as it has catalyzed reductions in test data volume and test application time of up to 100 times. This article sketches a brief history of test technology research, tracking the evolution of compression technology that has led to the success of scan compression. It is not our intent to identify specific inventors on a finegrained timeline. Instead, we present the important concepts at a high level, on a coarse timeline. Starting in 1998 and continuing to the present, numerous scan-compression-related inventions have had a major impact on the test landscape. However, this article also is not a survey of the various scan compression methods. Rather, we focus on the evolution of the types of constructs used to create breakthrough solutions.
Keywords
boundary scan testing; data compression; history; integrated circuit testing; logic testing; IC test; historical perspective; integrated circuit testing; scan compression technology; test pattern size reduction; Costs; Delay; Design for testability; Equations; History; Integrated circuit testing; Manufacturing; Multiplexing; Technological innovation; Time measurement; IC testing; scan compression; test application time reduction; test data volume reduction;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2008.40
Filename
4483808
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