Title :
Efficient FIR filter architectures suitable for FPGA implementation
Author :
Evans, Joseph B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
fDate :
7/1/1994 12:00:00 AM
Abstract :
This paper describes efficient architectures for FIR filters. By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA)
Keywords :
digital filters; logic arrays; FIR filter architectures; FPGA implementation; complexity; high sampling rate filters; powers-of-two coefficients; single field-programmable gate array; Arithmetic; Field programmable gate arrays; Finite impulse response filter; Frequency response; Logic arrays; Logic devices; Routing; Signal sampling; Space technology; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
