DocumentCode
1123863
Title
Efficient FIR filter architectures suitable for FPGA implementation
Author
Evans, Joseph B.
Author_Institution
Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
Volume
41
Issue
7
fYear
1994
fDate
7/1/1994 12:00:00 AM
Firstpage
490
Lastpage
493
Abstract
This paper describes efficient architectures for FIR filters. By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA)
Keywords
digital filters; logic arrays; FIR filter architectures; FPGA implementation; complexity; high sampling rate filters; powers-of-two coefficients; single field-programmable gate array; Arithmetic; Field programmable gate arrays; Finite impulse response filter; Frequency response; Logic arrays; Logic devices; Routing; Signal sampling; Space technology; Very large scale integration;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.298385
Filename
298385
Link To Document