Title :
On-chip high voltage charge pump in standard low voltage CMOS process
Author :
Hasan, T. ; Lehmann, T. ; Kwok, C.Y.
Author_Institution :
Dept of Eng., Univ. of Cambridge, UK
fDate :
7/21/2005 12:00:00 AM
Abstract :
An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 μm CMOS process is presented. For a 250 kΩ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.
Keywords :
CMOS integrated circuits; DC-DC power convertors; low-power electronics; 0.18 micron; 1.8 V; 250 kohm; 4VDD charge pump; CMOS devices; MOS transistors; low voltage CMOS process; on-chip high voltage charge pump; symmetrical architecture; voltage stress;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20051488
