• DocumentCode
    1124541
  • Title

    Low-voltage CMOS transconductance cell based on parallel operation of triode and saturation transconductors

  • Author

    Allen, P.E.

  • Volume
    30
  • Issue
    14
  • fYear
    1994
  • fDate
    7/7/1994 12:00:00 AM
  • Firstpage
    1124
  • Lastpage
    1126
  • Abstract
    A new linearity improvement technique for CMOS triode transconductors is presented. The idea is based on the parallel operation of CMOS triode and saturation region transconductors. Simulation results indicate that 0.01% THD and linearity is possible with 800 mV peak-to-peak input differential signals and 1.5 V supply voltage
  • Keywords
    CMOS integrated circuits; active networks; analogue processing circuits; linear integrated circuits; linearisation techniques; 1.5 V; LV CMOS transconductance cell; THD; linearity improvement technique; low-voltage cell; parallel operation; saturation region; saturation transconductors; triode transconductors;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19940756
  • Filename
    299342
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1124541