Author :
Singh, Jaswinder Pal ; Gupta, Anoop ; Levoy, Marc
Abstract :
Recently, a new class of scalable, shared-address-space multiprocessors has emerged. Like message-passing machines, these multiprocessors have a distributed interconnection network and physically distributed main memory. However, they provide hardware support for efficient implicit communication through a shared address space, and they automatically exploit temporal locality by caching both local and remote data in a processor´s hardware cache. In this article, we show that these architectural characteristics make it much easier to obtain very good speedups on the best known visualization algorithms. Simple and natural parallelizations work very well, the sequential implementations do not have to be fundamentally restructured, and the high degree of temporal locality obviates the need for explicit data distribution and communication management. We demonstrate our claims through parallel versions of three state-of-the-art algorithms: a recent hierarchical radiosity algorithm by Hanrahan et al. (1991), a parallelized ray-casting volume renderer by Levoy (1992), and an optimized ray-tracer by Spach and Pulleyblank (1992). We also discuss a new shear-warp volume rendering algorithm that provides the first demonstration of interactive frame rates for a 256/spl times/256/spl times/256 voxel data set on a general-purpose multiprocessor.<>
Keywords :
data visualisation; distributed memory systems; parallel algorithms; parallel programming; ray tracing; rendering (computer graphics); shared memory systems; distributed interconnection network; hierarchical radiosity algorithm; optimized ray-tracer; parallel visualization algorithms; parallelized ray-casting volume renderer; physically distributed main memory; shared-address-space multiprocessors; shear-warp volume rendering; temporal locality; Computer graphics; Data visualization; Hardware; Image generation; Layout; Ray tracing; Rendering (computer graphics); Silicon; Vehicles; Workstations;