Title :
Fast floorplanning by look-ahead enabled recursive bipartitioning
Author :
Cong, Jason ; Romesis, Michail ; Shinnerl, Joseph R.
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA
Abstract :
A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by the explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called partitioning to optimize module arrangement (PATOMA), generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time. Experiments on standard Gigascale Systems Research Center benchmarks compare PATOMA to the Capo macro placer, the Traffic floorplanner, and to both the default and high-effort modes of the Parquet 4.0 floorplanner. With all blocks hard, PATOMA´s average wirelength is comparable to the high-effort mode of Parquet 4.0 floorplanner and Capo, while PATOMA runs significantly faster. With all blocks soft, PATOMA produces wirelength 9% shorter on average than that of Parquet´s default mode, and PATOMA runs seven times faster. For a new set of benchmarks with a mix of 500 to 2000 hard and soft blocks, PATOMA produces results with wirelengths roughly half of Parquet´s, with a speedup of almost 200times
Keywords :
circuit layout CAD; circuit optimisation; logic CAD; logic partitioning; PATOMA; fast floorplanning; gigascale systems; look ahead enabled recursive bipartitioning; module arrangement; optimized partitioning; Application specific integrated circuits; Clustering algorithms; Computer science; Design automation; Design optimization; Integrated circuit interconnections; Law; Legal factors; Minimization methods; Timing; Floorplanning; optimization; partitioning; physical design;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.859519